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ST8004
Smartcard interface
General features

3V or 5V supply for the IC Step-up converter for VCC generation 3 specific protected half duplex bi-directional buffered I/O lines Automatic activation and deactivation sequences Thermal and short-circuit protections on all card contacts 26MHz integrated crystal oscillator Clock generation for the card up to 20MHz with synchronous frequency changes ISO7816-3 compatible Enhanced ESD protection on card side SO-28 package Under voltage lockout protection selectable to 3V or 2.2V Supply supervisor integrated
SO-28
Description
The ST8004 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification.
Order code
Part number ST8004CDR January 2007 Temperature range 0 to 85 C Package SO-28 (Tape & Reel) Rev 7 Packaging 1000 parts per reel 1/26
www.st.com
26
Contents
ST8004
Contents
1 2 3 4 5 6 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage supervisor (for VTHSEL = VDD or floating) . . . . . . . . . . . . . . . . . 15 Voltage supervisor (for VTHSEL = GND) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inactive state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
ST8004
Diagram
1
Figure 1.
Diagram
Block diagram
3/26
Pin configuration
ST8004
2
Figure 2.
Pin configuration
Pin connections
Table 1.
Pin N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4/26
Pin description
Symbol CLKDIV1 CLKDIV2 5V/3V PGND C1+ VDDP C1VUP PRES PRES I/O AUX2 AUX1 CGND CLK RST VCC VTHSEL CMDVCC Control of CLK Frequency Control of CLK Frequency VCC selection pin. Power Ground for Step-Up converter External Cap. for Step-Up converter Power Supply for Step-Up converter External Cap. Step-Up converter Output of Step-Up converter Card Presence Input (Active Low) Card Presence Input (Active High) Data Line to and from card (C7) (internal 10k pull-up resistor connected to VCC) Auxiliary line to and from card (C8) (internal 10k pull-up resistor connected to VCC) Auxiliary line to and from card (C4) (internal 10k pull-up resistor connected to VCC) Ground for card signal (C5) Clock to card (C3) Card Reset (C2) Supply Voltage for the card (C1) Deactivation threshold selector pin (under voltage lock-out) Start activation sequence input (Active Low) Name and function
ST8004 Table 1.
Pin N 20 21 22 23 24 25 26 27 28
Pin configuration Pin description
Symbol RSTIN VDD GND OFF XTAL1 XTAL2 I/OUC AUX1UC AUX2UC Card Reset Input from MCU Supply Voltage Ground Interrupt to MCU (active Low) Crystal or external clock input Crystal connection (leave this pin open if external clock is used) Data Line to and from MCU (internal 10k pull-up resistor connected to VDD) Auxiliary line to and from MCU (internal 10k pull-up resistor connected to VDD) Auxiliary line to and from MCU (internal 10k pull-up resistor connected to VDD) Name and function
5/26
Maximum ratings
ST8004
3
Table 2.
Symbol
Maximum ratings
Absolute maximum ratings
Parameter Min -0.3 -0.3 -0.3 Max 7 VDD + 0.3 VCC + 0.3 9 -6 -2 6 2 Unit V V V V KV KV
VDD, VDDP Supply voltage Vn1 Vn2 Vn3 ESD1 ESD2 Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, VTHSEL, CMDVCC, PRES, PRES and OFF Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK Voltage on pins VUP, S1 and S2 MIL-STD-883 class 3 on card contact pins, PRES and PRES (Note 1, 2) MIL-STD-883 class 2 on C contact pins and RSTIN (Note 1, 2)
Note: Note: 1 2
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All card contacts are protected against any short with any other card contact. Method 3015 (HBM, 1500 , 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
Thermal data
Parameter Thermal resistance junction-ambient temperature Condition In free air Value 70 Unit K/W
Table 3.
Symbol RthJA
Table 4.
Symbol TA
Recommended operating conditions
Parameter Temperature range Test Conditions Min. -25 Typ. Max. 85 Unit C
6/26
ST8004
Electrical characteristics
4
Table 5.
Symbol VDD
Electrical characteristics
Electrical characteristics over recommended operating (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Supply voltage Supply voltage for the voltage doubler Output voltage on pin VUP from step-up converter Input voltage to be applied on VUP in order to block the step-up converter Inactive mode IDD Supply current Active mode; fCLK = fXTAL; CL = 30pF Inactive mode Supply current for step-up Active mode; fCLK = fXTAL; converter CL = 30pF Threshold voltage on VDD VTHSEL = VDD or floating Threshold voltage on VDD VTHSEL = GND VTHSEL = VDD or floating VTHSEL = GND 6 VTHSEL = GND 5 1.5 0.1 ICC=0 ICC=65 mA 2.2 2.9 50 0 20 50 18 150 2.4 3.08 150 V V mV mV ms s mA Test Conditions VTHSEL = VDD or floating VTHSEL = GND Min. 2.7 3.150 4.5 To comply with VI(RIPPLE)(P-P) specifications 4.75 5.5 5 Typ. Max. 6.5 V 6.5 6.5 V 5.25 V Unit
VDDP VO(VUP)
VI(VUP)
7
9
V
1.2 mA
IP
Vth2 Vth3
VHYS(th2) Hysteresis on Vth2 VHYS(th3) Hysteresis on Vth3 tW THFIL Pulse width of the internal alarm pulse Delay of internal filter
7/26
Electrical characteristics
ST8004
Table 6.
Symbol
Card supply voltage characteristics (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C) (Note 1)
Parameter Test Conditions Inactive mode Inactive mode; ICC = 1 mA Active Mode; VDDP = 5V 5% 5 V card |ICC| < 65 mA DC 3 V card 5 V card 3 V card 5 V card 3 V card Min. -0.1 -0.1 4.75 2.85 4.65 2.85 4.65 2.76 Typ. Max. 0.1 0.4 5.25 3.15 5.25 3.15 5.25 3.15 350 65 mA VCC short circuit to GND Slew rate Up to down 0.11 150 0.22 V/s mV V Unit
VCC
Output voltage including ripple Active Mode; single current pulse of 100 mA; 2 s
Active Mode; current pulse of 40 nAs with |ICC|<200mA t < 400 ns VI(RIPPLE) Peak to peak ripple voltage on VCC (P-P) |ICC| SR Output current
20 KHz to 200 MHz, VDDP = 5V 5% From 0 to 5V or to 3V
Table 7.
Symbol CEXT fI(XTAL) VIH(XTAL) VIL(XTAL)
Crystal connection (pins XTAL1 and XTAL2) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Test Conditions Min. Typ. Max. 15 2 0.7 VDD 0 26 VDD 0.3 VDD Unit pF MHz V V
External capacitors on pins Depending on specification of XTAIL1, XTAIL2 crystal or resonator used Crystal Input Frequency High level input voltage on XTAIL1 Low level input voltage on XTAIL1
Table 8.
Symbol
Data lines (pins I/O, AUX1, AUX2, AUX1UC and AUX2UC) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz,unless otherwise noted. Typical values are to TA = 25C)
Parameter Test Conditions Min. Typ. 200 1 10 Max. Unit ns MHz pF
Delay between falling edge on pin I/O tD(EDGE) and I/OUC and width of active pull-up pulse fI/O(MAX) Maximum frequency of data lines CI Input capacitance on data lines
8/26
ST8004
Electrical characteristics
Table 9.
Data lines (pins I/O, AUX1 AND AUX2 WITH 10 k Pull-up resistor connected to VCC Internally (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Test Conditions Min. 0.75 VCC 0.9 VCC Typ. Max. VCC VCC+0.3 300 1.8 -0.3 No Load II/O = 1 mA -1 10 600 9 From VIL max to VIH min CO = 80 pF, no DC load; 0.4 V to 70% from 0 to VCC 13 1 0.1 10 VCC 0.8 0.1 V 0.3 mA A A K s s pF mV V V Unit V
Symbol VOH VOL VIH VIL VINACTIVE IEDGE |IIH| IIL RPU(INT) tT(DI) tT(DO) CI
High level output voltage on IOH = - 40A data lines No Load Low level output voltage on data lines High level input voltage on data lines Low level input voltage on data lines Voltage on data lines when inactive IOL = 1 mA
Current from data lines V = 0.7 x VCC; CO = 80 pF when active pull-up is active OH Input leakage current when high Low level input current Internal pull-up resistance to VCC Input transition times Output transition times Input capacitance VIH = VCC VIL = 0
Table 10.
Data lines (pins I/OUC, AUX1UC AND AUX2UC with 10 k Pull-up resistor connected to VDD internally (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted.Typical values are to TA = 25C)
Parameter High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Current when high Input Leakage Current when low Internal pull-up resistance to VDD VIH = VDD VIL = 0 9 11 Test Conditions IOH = - 40A No Load IOL = 1 mA Min. 0.75 VDD 0.9 VDD 0 0.7 VDD 0 300 VDD 0.3 VDD 10 600 13 mV V V A A K Typ. Max. VDD Unit V
Symbol VOH VOL VIH VIL |ILIH| IIL RPU(INT)
9/26
Electrical characteristics Table 10.
ST8004
Data lines (pins I/OUC, AUX1UC AND AUX2UC with 10 k Pull-up resistor connected to VDD internally (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted.Typical values are to TA = 25C)
Parameter Input transition times Output transition times Input capacitance Test Conditions From VIL max to VIH min CO = 30 pF, no DC load; 10% to 90% from 0 to VDD Min. Typ. Max. 1 0.1 10 Unit s s pF
Symbol tT(DI) tT(DO) CI
Table 11.
Symbol fOSC(INT)
Internal oscillator (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted.Typical values are to TA = 25C)
Parameter Frequency of internal oscillator Test Conditions Min. 2.2 Typ. Max. 3.2 Unit MHz
Table 12.
Symbol VO(INACTIVE) tD(RSTIN-RST) VOL VOH tR, tF
Reset output to the card (pin RST) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25C)
Parameter Output Voltage in Inactive Mode Delay between pins RSTN and RST Low Level Output Voltage High Level Output Voltage Rise and fall time (10% to 90% of VCC) Test Conditions IO = 1 mA No Load RST Enable IOL = 200 A IOH = -200 A CO = 250 pF 0 0.9 VCC Min. 0 0 Typ. Max. 0.3 V 0.1 2 0.2 VCC 0.1 s V V s Unit
Table 13.
Symbol
Clock output to the card (pin CLK) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Test Conditions IO = 1 mA No Load IOL = 200 A IOH = -200 A CO = 35 pF (Note 2) CO = 35 pF (Note 2) CO = 35 pF 45 0.2 Min. 0 0 0 0.9 VCC Typ. Max. 0.3 V 0.1 0.3 VCC 8 55 V V ns % V/ns Unit
VO(INACTIVE) Output Voltage in Inactive Mode VOL VOH tR, tF d SR Low Level Output Voltage High Level Output Voltage Rise and fall time (10% to 90% of VCC) Duty cycle factor (except for fXTALS) (See Note 4) Slew Rate (rise and fall edge)
10/26
ST8004
Electrical characteristics
Table 14.
Logic inputs (pins CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN and 5V/3V, VTHSEL (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25C) (Note 3)
Parameter Low Level Input Voltage High Level Input Voltage Input Leakage Current when high Input Leakage Current when low VIL = 0 to VDD VIH = 0 to VDD Test Conditions Min. 0 0.7 VDD Typ. Max. 0.3 VDD VDD 5 5 Unit V V A A
Symbol VIL VIH |ILIH| |ILIL|
Table 15.
OFF outputs (pin OFF is an open drain with an internal 20 k Pull-up resistor to VDD); (see note 5) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Low Level Output Voltage High Level Output Voltage Test Conditions IOL = 2 mA IOH = -15 A 0.75 VDD Min. Typ. Max. 0.4 Unit V V
Symbol VOL VOH
Table 16.
Symbol TSD ICC(SD)
Protection (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Shut down temperature Shut down current at VCC Test Conditions Min. Typ. 135 150 Max. Unit C mA
Table 17.
Symbol tACT tDE t3 t5
Timing (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to TA = 25C)
Parameter Activation sequence duration Test Conditions (See Figure 5.) 60 Min. Typ. 180 80 Max. 220 100 130 140 Unit s s s s
Deactivation sequence duration (See Figure 6.) Start of the windows to send CLK to card End of the windows to send CLK to card (See Figure 5.) (See Figure 5.)
Note:
1 2 3 4 5
To meet these specifications VCC should be decoupled to CGND using two ceramic multiplier capacitors of low ESR with values of 100nF. The transition time and duty cycle factor are shown in Figure 9.; d = t1/(t1+t2). PRES and CMDVCC are active Low; RSTIN and PRES are active High Referred to the paragraph "CLOCK CIRCUITRY" See paragraph "FAULT DETECTION".
11/26
Waveforms
ST8004
5
Waveforms
Figure 3. Alarm as a function of VDD (tW = 10 ms), VTHSEL = VDD or floating
Figure 4.
Alarm as a function of VDD (tW = 10 ms), VTHSEL = GND
12/26
ST8004 Figure 5. Activation sequence
Waveforms
Figure 6.
Deactivation sequence
13/26
Waveforms Figure 7. Behavior of OFF, CMDVCC, PRES and VCC
ST8004
Figure 8.
Emergency deactivation sequence
Figure 9.
Definition of output transition times
14/26
ST8004
Functional description
6
Functional description
Throughout this document it is assumed that the reader is familiar with iso7816 norm terminology
6.1
Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All interface signals with the microcontroller are referenced to VDD; therefore be sure the supply voltage of the microcontroller is also at VDD. All card contacts remain inactive during powering up or powering down. The sequencer is not activated until VDD reaches Vth2 +Vhys(th2) or Vth3 + Vhys(th3) when VTHSEL = GND. When VDD falls below Vth2 or Vth3, an automatic deactivation of the contacts is performed. To generate a 5 V 5% VCC supply to the card, an integrated voltage doubler is incorporated. This step-up converter should be separately supplied by VDDP and PGND (from 4.5 to 6.5 V). In order to satisfy the VI(RIPPLE)(P-P) specifications, VDDP should be from 4.75V to 5.25V. Due to large transient currents, the 2x100 nF capacitors of the step-up converter should have an ESR of less than 100 m and be located as near as possible to the IC. The supply voltages VDD and VDDP , may be applied to the IC in any time sequence. To get the correct deactivation of the card VDDP is allowed to turn-off only when VDD is below the undervoltage threshold. If a voltage between 7 and 9 V is available within the application, this voltage may be tied to pin VUP, thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the capacitor between pins S1 and S2 may be omitted.
6.2
Voltage supervisor (for VTHSEL = VDD or floating)
This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Figure 3.). As long as VDD is less than Vth2 +Vhys(th2), the IC will remain inactive whatever the levels on the command lines. This also lasts for the duration of tW after VDD has reached a level higher than Vth2 +Vhys(th2).The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth2, a deactivation sequence of the contacts is performed.
6.3
Voltage supervisor (for VTHSEL = GND)
This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Figure 6.). If VDD is less than Vth3 during a time, longer than THFIL (max 150s), the IC will remain inactive whatever the levels on the command lines. The IC remain inactive also for the duration of tw after VDD has reached a level higher than Vth3. The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth3 during time more than THFIL, a deactivation sequence of the contacts is performed.
15/26
Functional description
ST8004
6.4
Clock circuitry
The clock signal (CLK) to the card is either derived from a clock signal input on the pin XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2. The frequency may be chosen at fXTAL,1/2 fXTAL,1/4 fXTAL or 1/8 fXTAL via pins CLKDIV1 and CLKDIV2 (see Table 18.). The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width. In the case of fXTAL, the duty factors depend on the signal at XTAL1. In order to reach a 45% to 55% duty factor on the pin CLK the input signal on XTAL1 should have a duty factor of 48% to 52% and transition times of less than 5% of the input signal period.If a crystal is used with fXTAL, the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal characteristics and frequency. In the other cases, it is guaranteed between 45% and 55% of the period. The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing diagram of the activation sequence. If the signal applied to XTAL1 is controlled by the microcontroller, then the clock pulse will be applied to the card by the microcontroller after completion of the activation sequence. Table 18. Clock circuitry
CLKDIV1 0 0 1 1 CLKDIV2 0 1 1 0 CLK 1/8 fXTAL 1/4 fXTAL 1/2 fXTAL fXTAL
6.5
I/O Circuitry
The three data lines I/O, AUX1 and AUX2 are identical. The Idle state is realized by data lines I/O and I/OUC being pulled HIGH via a 10k resistor (I/O to VCC and I/OUC to VDD). I/O is referenced to VCC, and I/OUC to VDD, thus allowing operation with VCC VDD. The first line on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which then becomes the slave. After a time delay td (edge) (approximately 200 ns), the N transistor on the slave line is turned on, thus transmitting the logic 0 present on the master line.When the master line returns to logic 1, the P transistor on the slave line is turned on during the time delay td (edge) and then both lines return to their idle state. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA up to an output voltage of 0.9 VCC on a 80pF load. At the end of the active pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the load current. The maximum frequency on these lines is 1MHz.
16/26
ST8004
Functional description
6.6
Inactive state
After power-on reset, the circuit enters the inactive state. A minimum number of circuits are active while waiting for the microcontroller to start a session.

All card contacts are inactive (approximately 200 to GND); I/OUC, AUX1UC and AUX2UC are high impedance (10 k pull-up resistor connected to VDD) Voltage generators are stopped XTAL oscillator is running Voltage supervisor is active
6.7
Activation sequence
After power-on and, after the internal pulse width delay, the microcontroller may check the presence of the card with the signal OFF (OFF = HIGH while CMDVCC is High means that the card is present; OFF = LOW while CMDVCC is HIGH means that no card is present). If the card is in the reader (which is the case if PRES or PRES is true), the microcontroller may start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Figure 5.):

CMDVCC is pulled LOW (t0) The voltage doubler is started (t1~t0) VCC rises from 0 to 5 or 3V with a controlled slope (t2 = t1 +1/23T)(I/O, AUX1 and AUX2 follow VCC with a slight delay); T is 64 times the period of the internal oscillator, approximately 25s I/O, AUX1 and AUX2 are enabled (t3 = t1 +4T) CLK is applied to the C3 contact (t4) RST is enabled (t5 = t1 +7T).

The clock may be applied to the card in the following way: set RSTIN High before setting CMDVCC Low, and reset it Low between t3 and t5; CLK will start at this moment. RST will remain LOW until t5, where RST is enabled to be the copy of RSTIN. After t5, RSTIN has no further action on CLK. This is to allow a precise count of CLK pulses before toggling RST. If this feature is not needed, then CMDVCC may be set LOW with RSTIN Low. In this case, CLK will start at t3, and after t5, RSTIN may be set High in order to get the Answer To Request (ATR) from the card.
6.8
Active state
When the activation sequence is completed, the ST8004 will be in the active state. Data are exchanged between the card and the microcontroller via the I/O lines. The ST8004 is designed for cards without VPP (this is the voltage required to program or erase the internal non-volatile memory). Depending on the layout and on the application test conditions (for example with an additional 1pF cross capacitance between C2/C3 and C2/C7) it is possible that C2 is polluted with high frequency noise from C3. In this case, it will be necessary to connect a 220pF capacitor between C2 and CGND.
17/26
Functional description It is recommended to: 1. 2. 3. 4. Keep track C3 as far as possible from other tracks
ST8004
Have straight connection between CGND and C5 (the 2 capacitors on C1 should be connected to this ground track) Avoid ground loops between CGND,PGND and GND Decoupled VDDP and VDD separately; if the 2 supplies are the same in the application, then they should be connected in star on the main track.
With all these layout precautions, noise should be at an acceptable level, and jitter on C3 should be less than 100ps.
6.9
Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see Figure 6.):

RST goes LOW (t11 = t10) CLK is stopped LOW (t12 = t11 +1/2T) where T is approximately 25 s I/O, AUX1 and AUX2 are output into high-impedance state (t13 = t11 +T)(10 k pullup resistor connected to VCC) VCC falls to zero (t14 = t11 +1/23T); the deactivation sequence is completed when VCC reaches its inactive state VUP falls to zero (t15 = t11 +5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC remain pulled up to VDD via a 10 k resistor.
6.10
Fault detection
The following fault conditions are monitored by the circuit: Short-circuit or high current on VCC Removing card during transaction VDD dropping Overheating. There are two different cases (Figure 7.) 1. CMDVCC HIGH: (outside a card session) then, OFF is LOW if the card is not in the reader, and HIGH if the card is in the reader. A supply voltage drop on VDD is detected by the supply supervisor, which generates an internal power-on reset pulse, but does not act upon OFF. The card is not powered-up, so no short-circuit or overheating is detected. CMDVCC LOW: (within a card session) then, OFF falls LOW if the card is extracted, or if a short-circuit has occurred on VCC, or if the temperature on the IC has become too high. As soon as the fault is detected, an emergency deactivation is automatically performed (see Figure 8.). When the system controller sets CMDVCC back to HIGH, it may sense OFF again in order to distinguish between a hardware problem or a card extraction. If a supply voltage drop on VDD is detected while the card is activated, then an emergency deactivation will be performed and OFF goes LOW.
2.
18/26
ST8004
Functional description When OFF level falls low, the system controller must wait not less than 160s before setting high again the CMDVCC command. Depending on the type of card presence switch within the connector (normally closed or normal open), and on the mechanical characteristics of the switch, a bouncing may occur on presence signals at card insertion or withdrawal. There is no debounce feature in the device, so the software has to take it into account; however, the detection of card take off during active phase, which initiates an automatic deactivation sequence is done on the first True/False transition on PRES or PRES, and is memorized until the system controller sets CMDVCC High. So, the software may take some time waiting for presence switches to be stabilized without causing any delay on the necessary fast and normalized deactivation sequence.
19/26
Functional description Figure 10. ST8004 Sequencer
ST8004
20/26
ST8004 Figure 11. Card control sequencer
Functional description
CARD CONTROL
CHANGE_OFF
CM
CC =1
OFF = PRES or (not PRES_NEG)
act De
e
DV CC
DV
=1
CM
que nc
n tio iva
atio n Se
qu Se ce en
ctiv
CMDVCC=0 OFF_temp = 1
enc e
Dea
CMDVCC=0 OFF_temp = 0
d an er ad low re he lled n t pu 't i is isn CC V rd Ca CMD
LOCK_OFF_HIGH
Ac tiv
atio
nS
equ
LOCK_OFF_LOW
OFF=1
Removing Card after the Activation Sequence
OFF=0
CMDVCC=0 OFF_temp = 0
OFF_temp = PRES or (not PRES_NEG)
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Package mechanical data
ST8004
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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ST8004
Package mechanical data
SO-28 MECHANICAL DATA
mm. DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.40 0.50 17.70 10.00 1.27 16.51 7.60 1.27 0.291 0.020 18.10 10.65 0.1 0.35 0.23 0.5 45 (typ.) 0.697 0.393 0.050 0.650 0.300 0.050 0.713 0.419 TYP MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. TYP. MAX. 0.104 0.012 0.019 0.012 inch
8 (max.)
0016023
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Package mechanical data
ST8004
Tape & Reel SO-28 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 18.2 2.9 3.9 11.9 12.8 20.2 60 30.4 11.0 18.4 3.1 4.1 12.1 0.425 0.716 0.114 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.724 0.122 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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ST8004
Revision history
8
Table 19.
Date
Revision history
Revision history
Revision 5 6 7 Pag. 10, fig. 4, RSTIN ==> CLK. Order code has been updated and new template. Change values Vth3 Min. and Max. on Table 5. Changes
18-Mar-2004 04-May-2006 31-Jan-2007
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ST8004
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